Standard cascaded integrator comb digital filters are well known in the art. They may be used to perform an interpolation function. Interpolation acts to increase an inputted sample rate. In addition, when the positions of the cascaded integrator and cascaded comb sections have been exchanged, they can provide a decimation function. Decimation accomplishes a reduction of an inputted sample rate.
A decimation function is accomplished in such filters by first processing a received signal with a cascade of integrator stages. Following the last integrator stage, the rate is decimated or reduced by a rate change component. For example, if the rate is to be reduced to one-twentieth of the initial rate, the rate change component will accomplish the reduction by dropping nineteen consecutive samples and outputting each twentieth sample. A cascade of comb stages at the lowered rate then processes the samples output by the rate change component.
Cascaded integrator comb digital decimation filters are becoming widely used to reduce the sample rate of highly over-sampled, numerically represented analog signals. Such filters reduce the sample rate and suppress aliased signal folding interference. In addition, they can be configured to recover resolution sufficient to maintain the desired signal to noise ratio.
Unfortunately, the cascaded integrator comb digital decimation filter has a limited dynamic range when the over-sampling ratio is too low. An additional problem results from the fact that the integrator stages must operate at the higher, pre-decimated rate. This imposes a practical limitation on the data rate that can be input to the cascaded integrator stages. Further, such a structure requires higher speed, higher power and therefore more expensive components.
Various types of cascaded integrator comb digital filters have been disclosed in the art. Among these is a parallel cascaded integrator comb filter that is disclosed in U.S. Pat. No. 5,596,609 to Genrich et al. This filter, however, has an architecture that is fundamentally different from that of the present invention. The Genrich et al. architecture, for example, generates all possible decimated outputs in each stage of the integrator cascade. In addition, the hardware requirements of the Genrich et al. structure are significantly greater.
Consequently, there exists a need for an improved cascaded integrator comb digital filter having improved bandwidth control without requiring higher sample rates. Further, there exists a need for an improved cascaded integrator structure that reduces the input rate prior to processing by the integrator stages.